Because it is generally true that the fewer signals needed to test an IC the higher and more efficient the testing throughput for a batch of the ICs, IC design engineers strive to minimize the number of signals needed to test an IC. For example, suppose that an IC tester has sixty signal probes. If each of the ICs being tested requires twenty test signals, then the tester can test three ICs at a time. If, however, each of the ICs requires twenty one test signals, then the tester can test only two ICs at a time. Thus in this example, just one extra test signal per IC decreases the testing throughput by one third. Furthermore, in the latter case, the IC tester is significantly under utilized, and thus the testing is relatively inefficient with respect to the tester, because eighteen signal probes (60 - 42) are unused during each test cycle.
FIG. 1 is a schematic diagram of a portion of a reduced-signal-level dynamic random access memory (DRAM) circuit 10 such as a Direct Rambus.RTM. DRAM (RDRAM.RTM.) specified by Rambus Inc. of Mountain View, Calif. The memory circuit 10 includes one or more terminals 12.sub.0 -12.sub.n for receiving digital signals S.sub.0 -S.sub.n, a reference terminal 14 for receiving a reference voltage Vref, and clock terminals 16a and 16b for receiving complimentary Clock From Master signals CFM and CFM, respectively. Typically, Vref is half way between the logic 0 and logic 1 levels of S.sub.0 -S.sub.n to provide symmetrical noise margins. Also, CFM and CFM are typically derived from the rising and falling edges, respectively, of a single Master Clock (MC) signal (not shown) having a 50% duty cycle and the same frequency as CFM and CFM. In one embodiment, the signals S.sub.0 -S.sub.n have logic 0=1.8 volts (V) and logic 1=1.0V, Vref=1.4V, and CFM and CFM each have a frequency of 400 megahertz (MHz).
The memory circuit 10 also includes differential input buffers 18.sub.0 -18.sub.n and 20.sub.0 -20.sub.n for converting the voltage levels of S.sub.0 -SN into voltage levels that are compatible with the circuitry (not shown) internal to the memory circuit 10. These buffers are arranged in pairs [18.sub.0, 20.sub.0 ], . . . , [18.sub.n, 20.sub.n ] for alternately sampling the signals S.sub.0 -S.sub.n, respectively. Specifically, each buffer 18 receives a respective signal S on a non-inverting (+) terminal, Vref on an inverting (-) terminal, and CFM on a clock terminal 22. Similarly, each buffer 20 receives a respective signal S on a non-inverting terminal, Vref on an inverting terminal, and CFM on a clock terminal 24. Receiving the complimentary CFM and CFM signals instead of the MC signal provides the memory circuit 10 with two major advantages. First, although each buffer pair [18, 20] effectively samples a respective signal S on both the rising and falling edges--and thus at twice the frequency--of MC, each buffer of the pair operates at only half this sampling rate. Furthermore, each buffer of the pair is sensitive to the same clock-edge polarity, i.e., either rising or falling, and thus all the buffers 18 and 20 can have the same circuit design. Reducing the sampling rate of and using a single design for the buffers 18 and 20 often reduces the overall design and layout complexity of the memory circuit 10.
The memory circuit 10 also includes an IC package 21. The terminals 12.sub.0 -12.sub.n, 14, and 16a and 16b are disposed on the outside of the package 21, and the buffers 18.sub.0 -18.sub.n and 20.sub.0 -20.sub.n are disposed inside of the package 21.
In operation, using the input-buffer pair [18.sub.0 -20.sub.0 ] and the signal values given above as examples, the buffer 18.sub.0 samples So by comparing S.sub.0 to Vref in response to the rising edge of CFM. If S.sub.0 equals logic 0, i.e., 1.8 V, then the buffer 18.sub.0 generates a high output-voltage level, which the circuitry internal to the memory circuit 10 interprets as a logic 0. Conversely, if S.sub.0 equals logic 1, i.e., 1.0 V, then the buffer 18.sub.0 generates a low output-voltage level, which the circuitry internal to the memory circuit 10 interprets as a logic 1. The buffer 20.sub.0 samples S.sub.0 in response to the rising edge of CFM in a similar manner. The remaining input-buffer pairs [18.sub.1, 20.sub.1 ], . . . , [18.sub.n, 20.sub.n ] respectively sample S.sub.1 -S.sub.n in a similar manner.
Specific examples of the memory circuit 10 are described in more detail in the Advance Information sheet for the Direct RDRAM.RTM. 128/144-Mbit (256k.times.16/18.times.32S) and in other Rambus.RTM. publications, which are available from Rambus Incorporated of Mountain View, Calif. or from the Rambus website at www.rambus.com, and which are incorporated by reference herein.
Unfortunately, one must provide Vref to the terminal 14 during testing of the memory circuit 10 so that the differential input buffers 18 and 20 will function properly. Thus, as discussed above, providing Vref as a test signal may significantly lower the testing throughput and efficiency for a batch of the memory circuits 10.